Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface non-planarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, photolithographic patterning processes, where the positioning the image plane of the process surface within an increasingly limited depth of focus window is required to achieve high resolution semiconductor feature patterns.
In the formation of conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity and good electromigration resistance compared to other traditional interconnect metals such as aluminum. The undesirable contribution to electrical parasitic effects by metal interconnect residual resistivity has become increasingly important as device sizes have decreased. One problem with the use of copper relates to it relatively high degree of softness making it subject to relatively high differential material removal rates compared to adjacent dielectric insulating oxide materials during planarization processes such as chemical mechanical polishing (CMP).
Copper chemical mechanical planarization (CMP) is an important aspect of successful electrochemical deposition (ECD) processes where copper and copper barrier layers deposited overlying copper filled features are subsequently removed by a CMP planarization process. Both local and global planarization is critical to successful device operation especially with respect to forming overlying integrated device features. A recurring problem in copper CMP processes is that the simultaneous goal of achieving fast material removal rates of the copper and the underlying barrier layer without erosion of the underlying insulating dielectric layer or dishing of the copper filled feature is difficult to attain. Typically, the excess copper layer is removed following ECD according to a CMP process which generally includes an abrasive polishing slurry and a polishing pad applied with a significant down force to the semiconductor wafer surface. Typically multiple CMP polishing steps are used to first remove the copper layer followed by removal of the barrier layer to reveal an oxide layer and typically including a final oxide layer buffing step. In the prior art separate slurries are used for the individual CMP polishing steps to achieve the desired selectivity and removal rates. For example, it is frequently desirable to first use a slurry with a high copper removal rate to minimize the required polishing time for relatively thick overlayers of excess copper. The high removal rate slurry is then replaced with a low or medium removal rate slurry and polishing system including a different polishing pad to remove the barrier layer at a slower rate to reduce erosion of the underlying oxide layer and to reduce copper dishing.
The planarity of CMP processes is increasingly critical especially for devices having narrow semiconductor features such as line widths below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-level semiconductor device, including planarizing levels of a device containing both dielectric and metal portions to achieve local and global planarization for subsequent processing of overlying levels. Several semiconductor wafer defects are associated with non-planarities introduced during CMP polishing. For example, in CMP polishing of high polish rate materials such as copper features adjacent to an oxide surface, uniform polishing or local planarization is highly dependent on feature density. For example, the material removal rate is proportionally faster over larger surface areas of high polish rate material leading to dishing. In addition, a high pattern density (small pitch) of metal filled features adjacent to lower polish rate materials such as nitrides or oxides can lead to both dishing and erosion over the patterned area. Generally, erosion is defined as the thinning of the oxide layer thickness, for example, a low-k (low dielectric constant) oxide material including metal filled features, relative to an unpatterned or lower pattern density area. Dishing is defined as the reduced thickness of the metal feature from the lowest point of the feature relative to the adjacent oxide layer. Therefore the sum of the erosion and dishing represents total metal removal. Although erosion of narrow copper features in a relatively densely patterned area of a wafer process surface is known and various approaches have been proposed to reduce erosion, dishing of the relatively narrow line width copper features remains a problem which can degrade device electrical reliability and performance. One approach to improving planarity and reducing erosion has been to use slurries having higher selectivity's for material removal of the target layer with respect to an underlying layer.
For example, highly selective polishing slurries for polishing the various layers are available commercially and formulated for polishing the particular targeted polishing layer, for example a copper layer overlying an adhesion/barrier layer and a tantalum nitride (e.g., TaN) barrier layer overlying an oxide layer, for example an insulating dielectric layer or an oxide capping layer. High selectivity slurries may include various metal oxide abrasives including for example, silica (SiO2), alumina (Al2O3), ceria (CeO2), titania (TiO2), manganese dioxide (MnO2), and zirconia (ZrO2). In addition, complexing agents and surfactants are typically used to facilitate interaction of the slurry abrasive with the targeted polishing surface.
The increased use of lower strength low-k materials for the insulating dielectric layer, also referred to as an inter-layer dielectric (ILD) layer or inter-metal dielectric (IMD) layer, has led to increased vulnerability of oxide erosion resulting in surface topography variations caused by slurries having less than adequate selectivity with respect to an underlying layer, for example a TaN adhesion/barrier layer overlying an oxide based layer, for example an ILD layer, an anti-reflectance coating (ARC) layer, or an oxide capping layer. As pointed out, one approach in the prior art to reduce erosion of an underlying oxide layer has been to use slurries with a higher selectivity with respect to the underlying layer, for example in polishing a barrier layer overlying an oxide layer. One problem with this approach is that the high selectivity slurries formulated for polishing the particular layers frequently also have copper removal rates resulting in dishing of relatively narrow copper features leading to subsequent processing difficulties and device electrical performance degradation. Generally, both erosion and dishing lead to several subsequent processing difficulties such as forming overlying layer features with adequate integrated electrical connectivity, as well as optical resolution issues in photolithographic patterning steps. As such, it has been difficult to develop CMP polishing methods that can accomplish both requirements of reduced oxide layer erosion and copper feature dishing.
Therefore, there is a need in the semiconductor art for an improved CMP polishing method whereby a CMP polishing step including a CMP polishing slurry is better optimized for polishing copper filled features adjacent to an oxide surface to avoid the problems of dishing of the copper filled features while avoiding oxide erosion.
It is therefore an object of the invention to provide an improved CMP polishing method whereby a CMP polishing step including a CMP polishing slurry is better optimized for polishing copper filled features adjacent to an oxide surface to avoid the problems of dishing of the copper filled features while avoiding oxide erosion in addition to overcoming other shortcomings and deficiencies in the prior art.